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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
PD4664312-X
64M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
Description
The PD4664312-X is a high speed, low power, 67,108,864 bits (4,194,304 words by 16 bits) CMOS Mobile Specified RAM featuring Low Power Static RAM compatible function and pin configuration. The PD4664312-X is fabricated with advanced CMOS technology using one-transistor memory cell. The PD4664312-X is packed in 93-pin TAPE FBGA.
Features
* 4,194,304 words by 16 bits organization * Fast access time: 65, 75 ns (MAX.) * Fast page access time: 18, 25 ns (MAX.) * Byte data control: /LB (I/O0 to I/O7), /UB (I/O8 to I/O15) * Low voltage operation: 2.7 to 3.1 V (-B65X) 2.7 to 3.1 V (Chip), 1.65 to 2.1 V (I/O) (-BE75X) * Operating ambient temperature: TA = -25 to +85 C * Output Enable input for easy application * Chip Enable input: /CS pin * Standby Mode input: MODE pin * Standby Mode1: Normal standby (Memory cell data hold valid) * Standby Mode2: Density of memory cell data hold is variable
PD4664312
Access time ns (MAX.) Chip -B65X -BE75X Note 65 75 2.7 to 3.1 Operating supply voltage V I/O - Operating ambient temperature C -25 to +85 45 40 At operating mA (MAX.) Supply current At standby A (MAX.) Density of data hold 64M bits 16M bits 8M bits 4M bits 100 60 50 45 0M bit 10
2.7 to 3.1 1.65 to 2.1
Note Under development
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. M15867EJ5V0DS00 (5th edition) Date Published August 2002 NS CP (K) Printed in Japan
The mark
shows major revised points.
(c)
2001
PD4664312-X
Ordering Information
Part number Package Access time ns (MAX.) Chip Operating supply voltage V I/O - 1.65 to 2.1 Operating temperature C -25 to +85
PD4664312F9-B65X-CR2 PD4664312F9-BE75X-CR2
Note
93-pin TAPE FBGA (12 x 9)
65 75
2.7 to 3.1 2.7 to 3.1
Note Under development
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Preliminary Data Sheet M15867EJ5V0DS
PD4664312-X
Pin Configurations
/xxx indicates active low signal. 93-pin TAPE FBGA (12 x 9) [ PD4664312F9-B65X-CR2 ]
Top View Bottom View
10 9 8 7 6 5 4 3 2 1 A BCDE FGH J K LM N P PNM L K J HGF EDCBA
Top View
A 10 9 8 7 6 5 4 3 2 1 NC NC NC NC NC NC NC NC NC B NC NC C NC NC NC A11 A8 /WE NC /LB A7 NC A15 A12 A19 MODE NC /UB A6 A3 A21 A13 A9 A20 NC A18 A5 A2 D E F G NC NC A14 A10 NC NC A17 A4 A1 NC H NC A16 NC I/O6 NC NC I/O1 GND A0 NC NC I/O15 I/O13 I/O4 I/O3 I/O9 /OE NC GND I/O7 I/O12 VCC NC I/O10 I/O0 /CS I/O14 I/O5 NC I/O11 I/O2 I/O8 NC NC NC NC NC NC NC NC J K L M NC NC NC N NC NC P NC
A0 to A21 /CS MODE /WE /OE
: Address inputs : Chip Select : Standby mode : Write enable : Output enable
/LB, /UB VCC GND NC
Note
: Byte data select : Power supply : Ground : No Connection
I/O0 to I/O15 : Data inputs / outputs
Note Some signals can be applied because this pin is not internally connected. Remarks Refer to Package Drawing for the index mark.
Preliminary Data Sheet M15867EJ5V0DS
3
PD4664312-X
93-pin TAPE FBGA (12 x 9) [ PD4664312F9-BE75X-CR2 ]
Top View Bottom View
10 9 8 7 6 5 4 3 2 1 A BCDE FGH J K LM N P PNM L K J HGF EDCBA
Top View
A 10 9 8 7 6 5 4 3 2 1 NC NC NC NC NC NC NC NC NC B NC NC C NC NC NC A11 A8 /WE NC /LB A7 NC A15 A12 A19 MODE NC /UB A6 A3 A21 A13 A9 A20 NC A18 A5 A2 D E F G NC NC A14 A10 NC NC A17 A4 A1 NC H NC A16 NC I/O6 NC NC I/O1 GND A0 NC NC I/O15 I/O13 I/O4 I/O3 I/O9 /OE NC GND I/O7 I/O12 VCC NC I/O10 I/O0 /CS I/O14 I/O5 VCCQ I/O11 I/O2 I/O8 NC NC NC NC NC NC NC NC J K L M NC NC NC N NC NC P NC
A0 to A21 /CS MODE /WE /OE
: Address inputs : Chip Select : Standby mode : Write enable : Output enable
/LB, /UB VCC VCCQ GND NC
Note
: Byte data select : Power supply : Input / Output power supply : Ground : No Connection
I/O0 to I/O15 : Data inputs / outputs
Note Some signals can be applied because this pin is not internally connected. Remarks Refer to Package Drawing for the index mark.
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Preliminary Data Sheet M15867EJ5V0DS
PD4664312-X
Block Diagram
Standby mode control
VCC VCCQ GND Refresh counter A0 A21 Address buffer Row decoder Refresh control
Memory cell array 67,108,864 bits
I/O0 to I/O7 I/O8 to I/O15 Input data controller
Sense amplifier / Switching circuit
Column decoder
Output data controller
Address buffer
/CS MODE
/LB /UB /WE
/OE
Remark VCCQ is the input / output power supply for -BE75X.
Preliminary Data Sheet M15867EJ5V0DS
5
PD4664312-X
Truth Table
/CS MODE /OE /WE /LB /UB Mode I/O0 to I/O7 H x x L H H L H x x x H L x x x H H x H x x L L H H L L L H x H x x L H L L H L Not selected (Standby Mode 1) Not selected (Standby Mode 1) Not selected (Standby Mode 2) Output disable Word read Lower byte read Upper byte read Word write Lower byte write Upper byte write
Note
I/O I/O8 to I/O15 High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN
Supply current ISB1
High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN High-Z
ISB2 ICCA
Note MODE pin must be fixed to high level except Standby Mode 2. (refer to 2.3 Standby Mode Status Transition). Remark x: VIH or VIL, H: VIH, L: VIL
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Preliminary Data Sheet M15867EJ5V0DS
PD4664312-X
CONTENTS
1. Initialization .................................................................................................................................................................... 8 2. Partial Refresh ............................................................................................................................................................... 9 2.1 Standby Mode........................................................................................................................................................... 9 2.2 Density Switching...................................................................................................................................................... 9 2.3 Standby Mode Status Transition............................................................................................................................... 9 2.4 Addresses for Which Partial Refresh Is Supported ................................................................................................ 10 3. Page Read Operation .................................................................................................................................................. 11 3.1 Features of Page Read Operation .......................................................................................................................... 11 3.2 Page Length ........................................................................................................................................................... 11 3.3 Page-Corresponding Addresses............................................................................................................................. 11 3.4 Page Start Address................................................................................................................................................. 11 3.5 Page Direction ........................................................................................................................................................ 11 3.6 Interrupt during Page Read Operation.................................................................................................................... 11 3.7 When page read is not used................................................................................................................................... 11 4. Mode Register Settings................................................................................................................................................ 12 4.1 Mode Register Setting Method ............................................................................................................................... 12 4.2 Cautions for Setting Mode Register ........................................................................................................................ 13 5. Electrical Specifications ............................................................................................................................................... 14 6. Timing Charts............................................................................................................................................................... 20 7. Package Drawing ......................................................................................................................................................... 30 8. Recommended Soldering Conditions .......................................................................................................................... 31 9. Revision History ........................................................................................................................................................... 32
Preliminary Data Sheet M15867EJ5V0DS
7
PD4664312-X
1. Initialization
Initialize the PD4664312-X at power application using the following sequence to stabilize internal circuits. (1) Following power application, make MODE high level after fixing MODE to low level for the period of tVHMH. Make /CS high level before making MODE high level. (2) /CS and MODE are fixed to high level for the period of tMHCL. Normal operation is possible after the completion of initialization. Figure1-1. Initialization Timing Chart
Initialization Normal Operation
/CS (Input) tCHMH tVHMH MODE (Input) tMHCL
VCC
VCC (MIN.)
Cautions 1. Make MODE low level when starting the power supply. 2. tVHMH is specified from when the power supply voltage reaches the prescribed minimum value (VCC (MIN.)).
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Preliminary Data Sheet M15867EJ5V0DS
PD4664312-X
2. Partial Refresh
2.1 Standby Mode In addition to the regular standby mode (Standby Mode 1) with a 64M bits density, Standby Mode 2, which performs partial refresh, is also provided. 2.2 Density Switching In Standby Mode 2, the densities that can be selected for performing refresh are 16M bits, 8M bits, 4M bits, and 0M bit. The density for performing refresh can be set with the mode register. Once the refresh density has been set in the mode register, these settings are retained until they are set again, while applying the power supply. However, the mode register setting will become undefined if the power is turned off, so set the mode register again after power application. (For how to perform mode register settings, refer to section 4. Mode Register Settings.) 2.3 Standby Mode Status Transition In Standby Mode 1, MODE and /CS are high level, or MODE, /LB and /UB are high level. In Standby Mode 2, MODE is low level. In Standby Mode 2, if 0M bit is set as the density, it is necessary to perform initialization the same way as after applying power, in order to return to normal operation from Standby Mode 2. When the density has been set to 16M bits, 8M bits, or 4M bits in Standby Mode 2, it is not necessary to perform initialization to return to normal operation from Standby Mode 2. For the timing charts, refer to Figure 6-14. Standby Mode 2 (data hold: 16M bits / 8M bits / 4M bits) Entry / Exit Timing Chart, Figure 6-15. Standby Mode 2 (data not held) Entry / Exit Timing Chart.
Preliminary Data Sheet M15867EJ5V0DS
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PD4664312-X
Figure 2-1. Standby Mode State Machine
Power On
Initialization
Initial State
/CS = VIL
MODE = VIH
Active MODE = VIL
MODE = VIH, /CS = VIH or /LB, /UB = VIH /CS = VIL, MODE = VIH /CS = VIL, MODE = VIH
MODE = VIL
Standby Mode 1
MODE = VIL
Standby Mode 2 (16M bits / 8M bits / 4M bits)
MODE = VIL Standby Mode 2 (Data not held)
2.4 Addresses for Which Partial Refresh Is Supported
Data hold density 16M bits 8M bits 4M bits Correspondence address 000000H to 0FFFFFH 000000H to 07FFFFH 000000H to 03FFFFH
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Preliminary Data Sheet M15867EJ5V0DS
PD4664312-X
3. Page Read Operation
3.1 Features of Page Read Operation
Features Page length Page read-corresponding addresses Page read start address Page direction Interrupt during page read operation 8 Words Mode 8 words A2, A1, A0 Don't care Don't care Enabled Note
Note An interrupt is output when /CS = H or in case A3 or a higher address changes. 3.2 Page Length 8 words is supported as the page lengths. 3.3 Page-Corresponding Addresses The page read-enabled addresses are A2, A1, and A0. Fix addresses other than A2, A1, and A0 during page read operation. 3.4 Page Start Address Since random page read is supported, any address (A2, A1, A0) can be used as the page read start address. 3.5 Page Direction Since random page read is possible, there is not restriction on the page direction. 3.6 Interrupt during Page Read Operation When generating an interrupt during page read, either make /CS high level or change A3 and higher addresses. 3.7 When page read is not used Since random page read is supported, even when not using page read, random access is possible as usual.
Preliminary Data Sheet M15867EJ5V0DS
11
PD4664312-X
4. Mode Register Settings
The partial refresh density can be set using the mode register. Since the initial value of the mode register at power application is undefined, be sure to set the mode register after initialization at power application. When setting the density of partial refresh, data before entering the partial refresh mode is not guaranteed. (This is the same for resetup.) However, since partial refresh mode is not entered unless MODE = L when partial refresh is not used, it is not necessary to set the mode register. Moreover, when using page read without using partial refresh, it is not necessary to set the mode register. 4.1 Mode Register Setting Method The mode register setting mode can be entered by successively writing two specific data after two continuous reads of the highest address (3FFFFFH). The mode register setting is a continuous four-cycle operation (two read cycles and two write cycles). Commands are written to the command register. The command register is used to latch the addresses and data required for executing commands, and it does not have an exclusive memory area. For the timing chart and flow chart, refer to Figure 6-12. Mode Register Setting Timing Chart, Figure 6-13. Mode Register Setting Flow Chart. Table 4-1. shows the commands and command sequences. Table 4-1. Command sequence
Command sequence 1st bus cycle (Read cycle) Partial refresh density 16M bits 8M bits 4M bits 0M bit Address 3FFFFFH 3FFFFFH 3FFFFFH 3FFFFFH Data - - - - 2nd bus cycle (Read cycle) Address 3FFFFFH 3FFFFFH 3FFFFFH 3FFFFFH Data - - - - 3rd bus cycle (Write cycle) Address 3FFFFFH 3FFFFFH 3FFFFFH 3FFFFFH Data 00H 00H 00H 00H 4th bus cycle (Write cycle) Address 3FFFFFH 3FFFFFH 3FFFFFH 3FFFFFH Data 04H 05H 06H 07H
4th bus cycle (Write cycle)
I/O Mode Register setting 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 PL 1 PD 0
Page length
1
8 words
I/O1 I/O0 Partial refresh density 0 0 1 1 0 1 0 1
Density 16M bits 8M bits 4M bits 0M bit
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Preliminary Data Sheet M15867EJ5V0DS
PD4664312-X
4.2 Cautions for Setting Mode Register Since, for the mode register setting, the internal counter status is judged by toggling /CS and /OE, toggle /CS at every cycle during entry (read cycle twice, write cycle twice), and toggle /OE like /CS at the first and second read cycles. If incorrect addresses or data are written, or if addresses or data are written in the incorrect order, the setting of the mode register is not performed correctly. When the highest address (3FFFFFH) is read consecutively three or more times, the mode register setting entries are not performed correctly. (Immediately after the highest address is read, the setting of the mode register is not performed correctly.) Perform the setting of the mode register after power application or after accessing other than the highest address. Once the refresh density has been set in the mode register, these settings are retained until they are set again, while applying the power supply. However, the mode register setting will become undefined if the power is turned off, so set the mode register again after power application. For the timing chart and flow chart, refer to Figure 6-12. Mode Register Setting Timing Chart, Figure 6-13. Mode Register Setting Flow Chart.
Preliminary Data Sheet M15867EJ5V0DS
13
PD4664312-X
5. Electrical Specifications
Absolute Maximum Ratings
Parameter Symbol Condition -B65X Supply voltage Input / Output supply voltage Input / Output voltage Operating ambient temperature Storage temperature VCC VCCQ VT TA Tstg -0.5
Note Note
Rating -BE75X -0.5 Note to +4.0 -0.5 Note to +4.0
Note
Unit
-0.5
to +4.0
V V V C C
- to VCC + 0.4 (4.0 V MAX.) -0.5 -25 to +85 -55 to +125
to VCCQ + 0.4 (4.0 V MAX.) -25 to +85 -55 to +125
Note -1.0 V (MIN.) (Pulse width: 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions
Parameter Symbol Condition MIN. Supply voltage Input / Output supply voltage High level input voltage Low level input voltage Operating ambient temperature VCC VCCQ VIH VIL TA 2.7 - 0.8VCC -0.3
Note
-B65X MAX. 3.1 - VCC+0.3 0.2VCC +85 MIN. 2.7 1.65 0.8VCCQ -0.3
Note
-BE75X MAX. 3.1 2.1 VCCQ+0.3 0.2VCCQ +85
Unit
V V V V C
-25
-25
Note -0.5 V (MIN.) (Pulse width: 30 ns)
Capacitance (TA = 25C, f = 1 MHz)
Parameter Input capacitance Input / Output capacitance Symbol CIN CI/O VIN = 0 V VI/O = 0 V Test condition MIN. TYP. MAX. 8 10 Unit pF pF
Remarks 1. VIN: Input voltage, VI/O: Input / Output voltage 2. These parameters are not 100% tested.
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Preliminary Data Sheet M15867EJ5V0DS
PD4664312-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)
Parameter Symbol Test condition Density of data hold Input leakage current I/O leakage current ILI ILO VIN = 0 V to VCC VI/O = 0 V to VCC, /CS = VIH or /WE = VIL or /OE = VIH Operating supply current ICCA /CS = VIL, Minimum cycle time, II/O = 0 mA Standby supply current ISB1 /CS VCC - 0.2 V, MODE VCC - 0.2 V ISB2 /CS VCC - 0.2 V, MODE 0.2 V 16M bits 8M bits 4M bits 0M bit High level output voltage Low level output voltage VOH VOL IOH = -0.5 mA IOL = 1 mA 0.8VCC 0.2VCC 50 45 40 60 50 45 10 V V 64M bits 60 100 45 mA MIN. -1.0 -1.0 -B65X TYP. MAX. +1.0 +1.0 Unit
A A
A
Remark VIN: Input voltage, VI/O: Input / Output voltage DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2)
Parameter Symbol Test condition Density of data hold Input leakage current I/O leakage current ILI ILO VIN = 0 V to VCCQ VI/O = 0 V to VCCQ, /CS = VIH or /WE = VIL or /OE = VIH Operating supply current ICCA /CS = VIL, Minimum cycle time, II/O = 0 mA Standby supply current 40 mA MIN. -1.0 -1.0 -BE75X TYP. MAX. +1.0 +1.0 Unit
A A
ISB1
/CS VCC - 0.2 V, MODE VCC - 0.2 V
64M bits
60
100
A
ISB2
/CS VCC - 0.2 V, MODE 0.2 V
16M bits 8M bits 4M bits 0M bit
50 45 40
60 50 45 10
High level output voltage Low level output voltage
VOH VOL
IOH = -0.5 mA IOL = 1 mA
0.8VCCQ 0.2VCCQ
V V
Remark VIN: Input voltage, VI/O: Input / Output voltage
Preliminary Data Sheet M15867EJ5V0DS
15
PD4664312-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions [ -B65X ] Input Waveform (Rise and Fall Time 5 ns)
Vcc 0.8Vcc Vcc / 2 0.2Vcc GND 5ns Test points Vcc / 2
Output Waveform
Vcc / 2 Test points Vcc / 2
[ -BE75X ] Input Waveform (Rise and Fall Time 5 ns)
VccQ 0.8VccQ VccQ / 2 0.2VccQ GND 5ns Test points VccQ / 2
Output Waveform
VccQ / 2 Test points VccQ / 2
Output Load AC characteristics directed with the note should be measured with the output load shown in Figure 5-1, Figure 5-2. Figure 5-1. [ -B65X ] CL: 30 pF 5 pF (tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ)
ZO = 50 I/O (Output) I/O (Output)
Figure 5-2. [ -BE75X ] CL: 30 pF 5 pF (tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ)
ZO = 50
50
CL
50
CL
VCC / 2
VCCQ / 2
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Preliminary Data Sheet M15867EJ5V0DS
PD4664312-X
Read Cycle
Parameter Symbol MIN. Read cycle time Address access time /CS access time /OE to output valid /LB, /UB to output valid Output hold from address change Page read cycle time Page access time /CS to output in low impedance /OE to output in low impedance /LB, /UB to output in low impedance /CS to output in high impedance /OE to output in high impedance /LB, /UB to output in high impedance Address set to /OE low level /OE high level to address hold /CS high level to address hold /LB, /UB high level to address hold /CS low level to /OE low level /OE low level to /CS high level /CS high level pulse width /LB, /UB high level pulse width /OE high level pulse width tRC tAA tACS tOE tBA tOH tPRC tPAA tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tASO tOHAH tCHAH tBHAH tCLOL tOLCH tCP tBP tOP 0 -5 0 0 0 45 10 10 2 10,000 10,000 10 5 5 25 25 25 0 -5 0 0 0 45 10 10 2 10,000 10,000 5 18 18 10 5 5 25 25 25 65 65 65 45 65 5 25 25 -B65X MAX. MIN. 75 75 75 50 75 -BE75X MAX. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 3 3, 4 5 2 1 Unit Note
Notes 1. Output load: 30 pF 2. Output load: 5 pF 3. When tASO | tCHAH |, | tBHAH |, tCHAH and tBHAH (MIN.) are -15 ns.
tCHAH, tBHAH Address (Input)
/LB, /UB, /CS (Input)
/OE (Input) tASO
4. tBHAH is specified from when both /LB and /UB become high level. 5. tCLOL and tOP (MAX.) are applied while /CS is being hold at low level.
Preliminary Data Sheet M15867EJ5V0DS
17
PD4664312-X
Write Cycle
Parameter Symbol MIN. Write cycle time /CS to end of write Address valid to end of write /LB, /UB to end of write Write pulse width Write recovery time /CS pulse width /LB, /UB high level pulse width /WE high level pulse width Address setup time /OE high level to address hold /CS high level to address hold /LB, /UB high level to address hold Data valid to end of write Data hold time /OE high level to /WE set /WE high level to /OE set tWC tCW tAW tBW tWP tWR tCP tBP tWHP tAS tOHAH tCHAH tBHAH tDW tDH tOES tOEH 65 55 55 55 50 0 10 10 10 0 -5 0 0 30 0 0 10 10,000 10,000 -B65X MAX. MIN. 75 60 60 60 55 0 10 10 10 0 -5 0 0 35 0 0 10 10,000 10,000 -BE75X MAX. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 1 1, 2 Unit Note
Notes 1. When tAS | tCHAH |, | tBHAH | and tCP 18 ns, tCHAH and tBHAH (MIN.) are -15 ns.
tCHAH, tBHAH Address (Input)
/LB, /UB, /CS (Input)
/WE (Input) tAS
2. tBHAH is specified from when both /LB and /UB become high level. 3. tOES and tOEH (MAX.) are applied while /CS is being hold at low level.
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Preliminary Data Sheet M15867EJ5V0DS
PD4664312-X
Initialization
Parameter Power application to MODE low level hold /CS high level to MODE high level Following power application MODE high level hold to /CS low level Symbol tVHMH tCHMH tMHCL MIN. 50 0 200 MAX. Unit Note
s
ns
s
Standby Mode 2 Entry / Exit
Parameter Standby mode 2 entry /CS high level to MODE low level Standby mode 2 exit to normal operation MODE high level to /CS low level Standby mode 2 exit to normal operation MODE high level to /CS low level tMHCL2 200 tMHCL1 30 ns 1 Symbol tCHML MIN. 0 MAX. Unit Note ns
s
2
Notes 1. This is the time it takes to return to normal operation from Standby Mode 2 (data hold: 16M bits / 8M bits / 4M bits). 2. This is the time it takes to return to normal operation from Standby Mode 2 (data not held).
Preliminary Data Sheet M15867EJ5V0DS
19
PD4664312-X
6. Timing Charts
Figure 6-1. Read Cycle Timing Chart 1 (/CS Controlled)
tRC tRC
Address (Input) tACS
A1 tCHAH tACS
A2 tCHAH
A3
/CS (Input) tCP tCLZ /OE (Input) tCHZ tCLZ tCHZ tCP
/LB, /UB (Input)
I/O (Output)
High-Z Data Out Q1
High-Z Data Out Q2
High-Z
Remark In read cycle, MODE and /WE should be fixed to high level.
Figure 6-2. Read Cycle Timing Chart 2 (/OE Controlled)
tRC tRC
Address (Input)
A1
A2
A3
tAA /CS (Input) tASO /OE (Input) tOE
tBHAH
tAA
tBHAH
tOHAH
tASO
tOE
tOHAH
tASO
tOP /LB, /UB (Input) tOLZ High-Z Data Out Q1 tOHZ High-Z Data Out Q2 tOLZ tOHZ
tOP
I/O (Output)
High-Z
Remark In read cycle, MODE and /WE should be fixed to high level.
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Preliminary Data Sheet M15867EJ5V0DS
PD4664312-X
Figure 6-3. Read Cycle Timing Chart 3 (/CS, /OE Controlled)
tRC tRC
Address (Input)
A1 tAA
A2 tCHAH tBHAH tCHZ tASO tOE tOHAH
A3
tACS /CS (Input) tCLZ tCLOL /OE (Input) tOE
tOHAH tBHAH
tOHZ
tOHZ tOLZ /LB, /UB (Input) tOLZ
I/O (Output)
High-Z Data Out Q1
High-Z Data Out Q2
High-Z
Remark In read cycle, MODE and /WE should be fixed to high level.
Figure 6-4. Read Cycle Timing Chart 4 (Address Controlled)
tRC tRC
Address (Input) tAA
A1 tAA
A2
A3
/CS (Input)
/OE (Input)
/LB, /UB (Input) tOH tOH tOH
I/O (Output)
Data Out Q1
Data Out Q2
Remark In read cycle, MODE and /WE should be fixed to high level.
Preliminary Data Sheet M15867EJ5V0DS
21
PD4664312-X
Figure 6-5. Read Cycle Timing Chart 5 (/LB, /UB Controlled)
tRC tRC
Address (Input)
A1
A2
A3
/CS (Input)
/OE (Input) tBHAH tBHAH
/LB, /UB (Input) tBA tBLZ I/O (Output) High-Z tBHZ Data Out Q1
tBP tBA tBLZ High-Z tBHZ Data Out Q2
tBP
High-Z
Remark In read cycle, MODE and /WE should be fixed to high level.
Figure 6-6. Page Read Cycle Timing Chart
tRC Address (A3 to A21) (Input) AN tPRC AN+1 tPRC AN+2 tPRC AN+3 tPRC AN+4 tPRC AN+5 tPRC AN+6 tPRC AN+7
Page Address (A0 to A2) (Input) tOH
/CS (Input) tCHZ tOE
/OE (Input) tACS tOHZ tPAA tOH High-Z QN QN+1 QN+2 QN+3 QN+4 QN+5 QN+6 QN+7 tPAA tOH tPAA tOH tPAA tOH tPAA tOH tPAA tOH tPAA tOH
I/O (Output)
Remarks 1. In read cycle, MODE and /WE should be fixed to high level. 2. /LB and /UB are low level.
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Preliminary Data Sheet M15867EJ5V0DS
PD4664312-X
Figure 6-7. Write Cycle Timing Chart 1 (/CS Controlled)
tWC tWC
Address (Input) tAS
A1 tCW tWR tAS
A2 tCW tWR tAS
A3
/CS (Input) tCP tCP
/WE (Input)
/LB, /UB (Input) tOHAH tOES /OE (Input) tDW I/O (Input) High-Z tDH High-Z tDW tDH High-Z tOEH tASO
Data In D1
Data In D2
Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. In write cycle, MODE and /OE should be fixed to high level. Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB.
Preliminary Data Sheet M15867EJ5V0DS
23
PD4664312-X
Figure 6-8. Write Cycle Timing Chart 2 (/WE Controlled)
tWC tWC
Address (Input)
A1 tCHAH
A2 tCHAH
A3
tCW /CS (Input) tAS tWP
tCW
tWR
tCP
tAS
tWP
tWR
tCP
/WE (Input) tBHAH /LB, /UB (Input) tOHAH tOES /OE (Input) tDW I/O (Input) High-Z tDH
tWHP tBHAH
tASO tOEH
tDW High-Z
tDH High-Z
Data In D1
Data In D2
Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. In write cycle, MODE and /OE should be fixed to high level. Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB.
24
Preliminary Data Sheet M15867EJ5V0DS
PD4664312-X
Figure 6-9. Write Cycle Timing Chart 3 (/WE Controlled)
tWC tWC
Address (Input)
A1
A2
A3
tAW /CS (Input) tAS /WE (Input) tWHP tBHAH /LB, /UB (Input) tOHAH tOES /OE (Input) tDW I/O (Input) High-Z Data In D1 tDH High-Z tWP tWR tAS
tAW
tWP
tWR
tBHAH
tASO tOEH
tDW
tDH High-Z
Data In D2
Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. In write cycle, MODE and /OE should be fixed to high level. Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB.
Preliminary Data Sheet M15867EJ5V0DS
25
PD4664312-X
Figure 6-10. Write Cycle Timing Chart 4 (/LB, /UB Controlled)
tWC tWC
Address (Input)
A1
A2
A3
/CS (Input)
/WE (Input) tAS tBW tWR tAS tBW tWR
/LB, /UB (Input) tOHAH tOES /OE (Input) tDW I/O (Input) High-Z tDH
tBP
tBP tASO tOEH
tDW High-Z
tDH High-Z
Data In D1
Data In D2
Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. In write cycle, MODE and /OE should be fixed to high level. Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB.
26
Preliminary Data Sheet M15867EJ5V0DS
PD4664312-X
Figure 6-11. Write Cycle Timing Chart 5 (/LB, /UB Independent Controlled)
tWC tWC
Address (Input)
A1
A2
A3
/CS (Input)
/WE (Input) tAS tBW tWR
/LB (Input) tAS tBW tWR
/UB (Input) tOHAH tOES /OE (Input)
tBP tASO tOEH
tDW I/O0 to I/O7 (Input) High-Z
tDH High-Z
Data In D1
tDW I/O8 to I/O15 (Input) High-Z
tDH High-Z
Data In D2
Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. In write cycle, MODE and /OE should be fixed to high level. Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB.
Preliminary Data Sheet M15867EJ5V0DS
27
PD4664312-X
Figure 6-12. Mode Register Setting Timing Chart
Mode Register Setting tRC Address (Input) 3FFFFFH tRC 3FFFFFH tWC 3FFFFFH tWC 3FFFFFH
/CS (Input)
/OE (Input) tWP /WE (Input) tDW I/O (Input) High-Z tDH High-Z tDW tDH High-Z tWR tWP tWR
xxxxH
xxxxH
/LB, /UB (Input)
Figure 6-13. Mode Register Setting Flow Chart
Start
No
Address= 3FFFFFH Read with toggled the /CS, /OE
No
Address= 3FFFFFH Read with toggled the /CS, /OE
No
Address = 3FFFFFH Write
Data = 00H?
No
No
Address = 3FFFFFH Write No
Fail
Mode register setting exit
Data = xxH?
Note
End
Note xxH = 04H, 05H, 06H, 07H
28
Preliminary Data Sheet M15867EJ5V0DS
PD4664312-X
Figure 6-14. Standby Mode 2 (data hold: 16M bits / 8M bits / 4M bits) Entry / Exit Timing Chart
MODE (Input)
tCHML
tMHCL1
/CS (Input)
Standby mode 1
Standby mode 2 (Data hold: 16M bits / 8M bits / 4M bits)
Figure 6-15. Standby Mode 2 (data not held) Entry / Exit Timing Chart
MODE (Input)
tCHML
tMHCL2
/CS (Input)
Standby mode 1
Standby mode 2 (Data not held)
Preliminary Data Sheet M15867EJ5V0DS
29
PD4664312-X
7. Package Drawing
93-PIN TAPE FBGA (12x9)
E
wSB
ZD
ZE
B
A
D
10 9 8 7 6 5 4 3 2 1 PNM L K J HG F E DC B A
INDEX MARK
wSA
A y1 S A2 S
ITEM D E w e A A1 A2
MILLIMETERS 9.00.1 12.00.1 0.2 0.8 1.30.1 0.160.05 1.14 0.400.05 0.08 0.1 0.2 0.9 0.8 P93F9-80-CR2
y
S
e
A1 S AB
b x y y1 ZD ZE
b
x
M
30
Preliminary Data Sheet M15867EJ5V0DS
PD4664312-X
8. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the PD4664312-X. Type of Surface Mount Device
PD4664312F9-CR2: 93-pin TAPE FBGA (12 x 9)
Preliminary Data Sheet M15867EJ5V0DS
31
PD4664312-X
9. Revision History
Edition/ Date 5th edition/ Aug. 2002 Modification Supply Voltage (Chip) p.1 pp.1, 15 p.17 p.20 p.21 p.1 pp.1, 15 pp.17, 18 p.22 p.23 Deletion Features This edition Page Previous edition Type of revision Deletion Class Location Description (Previous edition This edition) -C75X, -C85X, -E85X, -E10X, -BE85X, -CE80X, -CE90X 2.6 to 3.1 V 2.7 to 3.1 V Fast access time: 80, 85, 90, 100 ns Fast page access time: 30, 35 ns Modification Operating supply current Addition Read Cycle -BE75X: TBD 40 mA tOP (MIN.): 2ns Timing charts are modified. Timing charts are modified.
Throughout Throughout
Modification Figure 6-2 Modification Figure 6-3
32
Preliminary Data Sheet M15867EJ5V0DS
PD4664312-X
[ MEMO ]
Preliminary Data Sheet M15867EJ5V0DS
33
PD4664312-X
[ MEMO ]
34
Preliminary Data Sheet M15867EJ5V0DS
PD4664312-X
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Preliminary Data Sheet M15867EJ5V0DS
35

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